The present invention relates to the technology of restraining power consumption in a data processor incorporating a logical cache memory and an address translation mechanism, and more particularly to technology effectively applicable to, for example, microcomputers or microprocessors.
In order to improve the performance of data processors, an approach has been made to incorporating a cache memory in such a data processor. In a field where operating systems (hereinafter also called "OS") are used for controlling memories without causing users to become conscious of physical memories or real memories, data processors are required to support address translation mechanisms. The address translation mechanism is a mechanism for translating logical addresses (or virtual addresses) into physical addresses to implement virtual memory.
Heretofore, there has also been adopted the technology of incorporating in a data processor a translation lookaside buffer (hereinafter simply called "TLB" too)) for retaining a translation pair of logical/physical addresses to run an address translation mechanism at high speed. Although the cache memory and TLB are required for improving data processing performance and supporting OS, importance is also attached to deterring TLB from operating as much as possible in parallel to the operation of the cache memory as far as restraining an increase in power consumption is concerned. Therefore, the physical cache memory retaining a pair of physical address information and data as cache entries will have to make a search address a physical address by regularly gaining access to TLB, which will result in increasing the power consumption, however. On the other hand, the logical cache memory retaining a pair of logical address information and data as cache entries will be allowed to make the search address a logical address by gaining access to TLB only at the time of a cache miss. Consequently, the logical cache memory is considered advantageous to the physical cache memory in view of a reduction in power consumption. Notwithstanding, the logical cache memory has posed the problem of a synonym.
The synonym will subsequently be described. First, each task in a multi-task OS has processes as a run environment. The processes includes the state of a data processor, an address space, and an address translation table for use in translating a logical address into a physical address. As shown in FIG. 3, for example, a logical address A is translatable into a physical address C in a process 1 and into a physical address D in a process 2; in other words, the contents of TLB ought to be altered when process-to-process switching is conducted in such a multiple physical address space. If, however, the entry is replaced each time the process-to-process switching is carried out by invalidating the contents of TLB, not only processing time but also power consumption will increase to the extent that such an increase cannot be disregarded.
For the reason stated above, an address space identifier (ASID) concept is introduced as shown in FIG. 4A, so that the logical address in the process 1 and the logical address in the process 2 are distinguished from each other by extending the logical address by means of the address space identifier. It becomes thus unnecessary to invalidate TLB each time the process-to-process switching is carried.
When the address space identifier is used to extend the logical address, there may arise a case where the processes 1, 2 share a physical address space between them as shown in FIG. 5; more specifically, there arises a case where the logical address A in the process 1 and the logical address B in the process 2 are translated into the same physical address C. The above case where the same physical address is assigned to different logical addresses is called a synonym.
Referring to FIGS. 6A, 6B, a description will subsequently be given of the problem caused by a synonym in the logical cache memory. Since the logical addresses A and B are different, two entries whose data are considered the same may exist simultaneously in the logical cache memory as shown in FIG. 6A. Now assuming that the data C assigned to the logical address B is changed to data D when what has been assigned to the logical address B is rewritten in that state as shown in FIG. 6B, though the data on the main memory corresponding to the address B is rewritten to D in the write-through manner, the data assigned to the logical address A on the cache memory corresponding thereto remains to be C, which mismatches the cache memory and the data stored in the main memory. When the reading of the data assigned to the logical address A occurs further, a cache hit takes place and the data C is used. The problem of a synonym thus arises.
In order to solve the problem of a synonym, a share flag concept may be introduced. The share flag is, for example, a flag for indicating whether a predetermined physical address space or data therein is commonly used in a plurality of different processes or logical address spaces. As shown in FIG. 4B, such a share flag SH is attached to the cache entry of a logical cache memory. When the data contained in the entry of the logical cache memory is shared data, the share flag SH is set to "1", and "0" when it is not.
A logical cache memory in a set-associative form in a case where such a share flag concept has been adopted is assumed to be in the state of FIG. 2.
When a logical address b (VA(b) represents logical page information such as a logical page number) is accessed in that state and when the entry selected thereby is a cache miss, that is, when the tag VA(a) of the entry thus selected does not represent the logical page information VA(b) assigned to the logical address b with the share flag SH of the entry being 1, a procedure below is to be followed without the addition of a new entry. Namely, the logical address b as a search address of the cache memory is subjected to address translation by means of TLB to obtain its physical address information PA(b). Further, the logical page information VA(a) of the tag selected then is used for address translation by means of TLB likewise to obtain physical address information PA(a). When a comparison of both bits of physical address information results in a good match, that is PA(a)=PA(b), this means that the logical address b shares data with the logical address a and the cache entry is processed as a cache hit. Consequently, a plurality of data are prevented from existing at the same physical address in the logical cache memory and the problem of the synonym can thus be solved.
Incidentally, Japanese Unexamined Patent Publication No. 302444/1989 discloses the art of subjecting to address translation two logical addresses in the tag portion of the cache as well as a search address when the reading of the cache memory has proved the presence of shared data, and comparing both so as to deal with a cache hit on condition that the result of the comparison is proved to be conformity.